週次 |
日期 |
單元主題 |
第1週 |
|
Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra |
第1週 |
|
Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra |
第2週 |
|
Ch 2 Boolean AlgebraCh 3 Boolean Algebra (cont’d) |
第3週 |
|
Ch 4 Application of Boolean Algebra |
第4週 |
|
Ch 5 Karnaugh Maps |
第5週 |
|
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
第6週 |
|
Quiz 1
Ch 8 Combinational Ckt Design (skip 8.1, 8.2) |
第7週 |
|
Ch 8 (cont’d)
Ch 9 Multiplexers Decoders and PLD (skip 9.7) |
第8週 |
|
Ch 9 (cont’d)
Verilog: Combinational Circuits (3:30-6:00pm) |
第9週 |
|
Midterm |
第10週 |
|
Ch 11 Latches and FF |
第11週 |
|
Ch 12 Registers and Counters |
第12週 |
|
Ch 13 Analysis of Clock Sequential Ckts |
第13週 |
|
Ch 14 Derivation of State Graphs and Tables
( Skip examples 2 and 3 in Sec. 14.3) |
第14週 |
|
Quiz 2
Ch 15 Reduction of State Tables (15.1, 15.2) |
第15週 |
|
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
第16週 |
|
Ch 18 Circuits for Arithmetic Op. (18.1-18.2)
1/1 元旦放假一天 |
第17週 |
|
Supplementary materials |